1. Field of the Invention
The present invention relates to techniques for predicting manufacturing yield for integrated circuit chips. More specifically, the present invention relates to a method and apparatus for predicting manufacturing yield for integrated circuit chips based on hotspots and hotspot-related information collected within the integrated circuit chips.
2. Related Art
Dramatic improvements in semiconductor integration circuit (IC) technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor IC chip. These improvements in integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies, which have recently achieved ultra-deep-submicron feature sizes.
On the flip side, the constant drive towards ever-decreasing feature sizes has led to a significant increase in manufacturing costs. One of the main causes of the increasing manufacturing costs is a significant decrease in manufacturing yield. Therefore, it is extremely desirable to be able to predict manufacturing yield at the design stage. A methodology that performs yield prediction and evaluation at the design stage is referred to as “design for manufacturability” (DFM).
Note that DFM can be used to improve design-related manufacturing yield for IC chips. More specifically, DFM facilitates identifying problematic regions in a chip layout from manufacturing yield perspective. This enables corrections and improvements to be made during the design stage to improve the ultimate manufacturing yield. Furthermore, the yield prediction and evaluation can facilitate formulating an objective function associated with the yield, wherein the objective function can be used for yield-aware layout optimization.
The IC manufacturing process can be viewed as a function. The inputs of this function typically include process parameters and chip layout patterns, and the outputs of this function are the physical variable values. By definition, a chip yield associated with a specific process-related physical variable is the probability that the variable values fall inside the manufacturing specifications (i.e., an upper bound and a lower bound) at all locations within the chip. For example, a chemical mechanical polishing (CMP) process-induced yield can be defined as the probability of a topography thickness being inside the specifications. We refer to these process-related physical variables as “yield-indicative variables” because their values can be used to extract the manufacturing yield. Also note that the yield associated with the process parameters and the chip layout patterns is a “systematic yield,” which is distinct from a “random yield,” such as random-partial-related yield.
IC manufacturing processes typically involve complex physical and chemical interactions. Because it is impossible to control these complex physical and chemical interactions perfectly, yield-indicative variable values tend to fluctuate around corresponding nominal values, leading to systematic yield loss. Complementary to the yield definition, yield loss associated with a yield-indicative variable is defined as the probability that the yield-indicative variable values fall outside the manufacturing specifications/bounds. Note that CMP-induced yield losses and lithography printability induced yield losses have become two of the significant systematic yield loss sources that result from the continuing reductions in IC feature sizes.
One existing approach for yield/loss prediction is the cumulative distribution function (CDF) approach. The CDF approach relies on having precise knowledge of both the distributions of a given yield-indicative variable at all chip locations and spatial correlations between these distributions. If such knowledge is available, a joint CDF can then be derived for this yield-indicative variable. Next, the total chip yield can be computed based on the derived joint CDF function. However, the feasibility of the CDF approach for predicting yield depends on the availability of the yield-indicative variable distributions.
Unfortunately, it is very difficult to perform yield prediction using the CDF approach because of the difficulties in obtaining the yield-indicative variable distributions. These difficulties arise for a number of reasons. (1) Precise process parameter distributions are extremely difficult to obtain due to both technical difficulties and proprietary information issues. (2) Process parameters affect the values and distributions of the yield-indicative variables through a highly nonlinear process. Hence, even if the precise distributions of the process parameters can be obtained, they are substantially different from the distributions of the yield-indicative variables. For example, if the process parameter has a Gaussian distribution, the yield-indicative variables will typically have a non-Gaussian distribution. (3) The chip layout patterns also affect the values and distributions of the yield-indicative variables. Therefore, even if the process parameters are the same across an entire chip, the responses of the yield-indicative variable values at different chip locations can be different because of the different layout patterns. Consequently, the distributions of the yield-indicative variables at different chip locations can be different.
Because raw measurement data of the yield-indicative variables are extremely difficult to obtain from the fabrication plant (FAB) due to both technical difficulties and proprietary information issues, people tend to make assumptions and approximations about this data in order to use the CDF approach. Unfortunately, the errors introduced by these assumptions are typically quite unstable and unpredictable.
Hence, what is needed is a method and an apparatus for predicting IC manufacturing yield without the above-described problems.